FAC-V: An FPGA-Based AES Coprocessor for RISC-V

In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling deployment custom-tailored IoT solutions for handling different application requirements and workloads. Combined with open RISC-V Instruction Set Architecture (ISA), FPGA provides endless opportunities to create reconfigurable devices accelerators coprocessors tightly loosely coupled processor. When connecting Internet, secure communications data exchange are major concerns. However, adding security features requires extra capabilities from already resource-constrained devices. This article presents FAC-V coprocessor, which an FPGA-based solution processor that can be deployed following two coupling styles. implements in hardware Advanced Encryption Standard (AES), one most widely used cryptographic algorithms low-end devices, at cost few resources. The conducted experiments demonstrate achieve performance improvements several orders magnitude when compared software-only AES implementation; e.g., encrypting a message 16 bytes AES-256 reach gain around 8000× energy consumption 0.1 μJ.